The initial concepts and specifications for the adaptive integrated circuit deisgns of the ADDAPT transceiver have been published in the deliverable report D5.1. The design includes the main circuits of laserdiode driver (LDD), transimpedance amplifier (TIA), limiting amplifier (LA) and clock- and data-recovery (CDR). These ICs will be designed in 14 nm CMOS technology for high speed with data rates up to 56 Gb/s and lowest power consumption to achieve a high energy efficiency of all together a few pJ/bit. Furthermore, adaptivity with regard to performance (e.g. bandwidth) and power consumption scaling is implemented into the circuits. A rapid switch on/off faster than 20 ns and an adaptive performance tuning for data rates of 56-28-14-7 Gb/s enable the reduction of the power consumption in the optical link. Preliminary simulations revealed that a 50 % energy saving is possible by reducing the bandwidth by 50-70 %. The design of the circuits already started and a first 14 nm CMOS tape-out is expected at the end of 2014. Optionally, 28 nm CMOS might be used for additional circuits to verify basic circuit and adaptivity approaches.
More information can be found in the ‘Deliverables‘ section.