Objectives

Adaptivity:

  • Power saving factor based on smart switching up to 10 for a link with 12 paths and upt to 4 for a link with 4 paths
  • Power saving factor based on smart tuning up to 2 for the analog/mixed signal components (including VCSEL)
  • Combined power saving factor up to 20 by data rate scaling 0.672 Tb/s – 7Gb/s for 12 link paths or upt to 7 by data rate scaling 0.224 Tb/s – 7 Gb/s for 4 link paths

Optics:

  • Low-cost VCSEL with near-field coupling for up to 56 Gb/s, only 5 mA average bias current
  • Modulation power savings ≥ 50 % at minimum data rates (7 Gb/s)
  • Low-cost PD with near-field coupling, 56 Gb/s, >90 % coupling efficiency, 0.6 A/W sensitivity

ICs:

  • Reduction of energy consumption per bit including TIA, LDD and CDR by at least 30 % using advanced 32 nm CMOS
  • High speed up to 56 Gb/s
  • Goal is ~2 pJ/bit at 56 Gb/s (dependent on the application)

Packaging/Assembling:

  • Capable of data rates up to 56 Gb/s
  • Enable small pitch sizes
  • Verification platform of 12 links for up to 0.672 Tb/s or 4 links up to 0.224 Tb/s and ≤ 10 m length